Electronic components within a system may use serializer/de-serializer circuitry to transmit data by way of high-speed serial links. Such high-speed serial links allow for point-to-point data transfers to be made without the need to obtain access to a shared parallel bus. In order to increase the available bandwidth of a point-to-point link, multiple serial lanes may be included in the link.
A high-speed interface with multiple serial lanes needs transmitter lane alignment to allow the receiver partner to restore striped data from the multiple lanes. Sufficient buffer margins for the lanes are needed to avoid underflow and overflow of the transmitter lane buffers. However, large buffer margins results in long latencies.